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sdls025b ? december 1983 ? revised october 2003 1 post office box 655303 ? dallas, texas 75265 package options include plastic small-outline (d, ns, ps), shrink small-outline (db), and ceramic flat (w) packages, ceramic chip carriers (fk), and standard plastic (n) and ceramic (j) dips also available as dual 2-input positive-nand gate in small-outline (ps) package sn5400 ...j p ackage sn54ls00, sn54s00 ...j or w p ackage SN7400, sn74s00 . . . d, n, or ns package sn74ls00 . . . d, db, n, or ns package (top view) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1a 1b 1y 2a 2b 2y gnd v cc 4b 4a 4y 3b 3a 3y sn5400 ...w p ackage (top view) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1a 1b 1y v cc 2y 2a 2b 4y 4b 4a gnd 3b 3a 3y sn74ls00, sn74s00 ...ps p ackage (top view) 1 2 3 4 8 7 6 5 v cc 2b 2a 2y 1a 1b 1y gnd 3212019 910111213 4 5 6 7 8 18 17 16 15 14 4a nc 4y nc 3b 1y nc 2a nc 2b 1b 1a nc 3y 3a v 4b 2y gnd nc sn54ls00, sn54s00 . . . fk package (top view) cc nc ? no internal connection description/ordering information these devices contain four independent 2-input nand gates. the devices perform the boolean function y = a ? b or y = a + b in positive logic. copyright ? 2003, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
sdls025b ? december 1983 ? revised october 2003 2 post office box 655303 ? dallas, texas 75265 description/ordering information (continued) ordering information t a package ? orderable part number top-side marking SN7400n SN7400n pdip ? n tube sn74ls00n sn74ls00n pdip ? n tube sn74s00n sn74s00n tube SN7400d 7400 tape and reel SN7400dr 7400 soic ? d tube sn74ls00d ls00 soic ? d tape and reel sn74ls00dr ls00 0 c to 70 c tube sn74s00d s00 0 c to 70 c tape and reel sn74s00dr s00 SN7400nsr SN7400 sop ? ns tape and reel sn74ls00nsr 74ls00 sop ? ns tape and reel sn74s00nsr 74s00 sop ? ps tape and reel sn74ls00psr ls00 sop ? ps tape and reel sn74s00psr s00 ssop ? db tape and reel sn74ls00dbr ls00 snj5400j snj5400j cdip ? j tube snj54ls00j snj54ls00j cdip ? j tube snj54s00j snj54s00j ?55 c to 125 c snj5400w snj5400w ?55 c to 125 c cfp ? w tube snj54ls00w snj54ls00w cfp ? w tube snj54s00w snj54s00w lccc ? fk tube snj54ls00fk snj54ls00fk lccc ? fk tube snj54s00fk snj54s00fk ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. function table (each gate) inputs output a b output y h h l l xh x l h logic diagram, each gate (positive logic) a b y
sdls025b ? december 1983 ? revised october 2003 3 post office box 655303 ? dallas, texas 75265 schematic ?00 gnd y 130 ? v cc 4 k ? a 1.6 k ? 1 k ? b v cc resistor values shown are nominal. y gnd 3 k ? 4 k ? 120 ? 8 k ? 20 k ? 1.5 k ? 12 k ? a b 2.8 k ? 900 ? b a 500 ? 250 ? 3.5 k ? ?ls00 ?s00 v cc y gnd 50 ?
sdls025b ? december 1983 ? revised october 2003 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? supply voltage, v cc (see note 1) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage: ?00, ?s00 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?ls00 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): d package 86 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . db package 96 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n package 80 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ns package 76 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ps package 95 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. voltage values are with respect to network ground terminal. 2. the package termal impedance is calculated in accordance with jesd 51-7. recommended operating conditions (see note 3) sn5400 SN7400 unit min nom max min nom max unit v cc supply voltage 4.5 5 5.5 4.75 5 5.25 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v i oh high-level output current ?0.4 ?0.4 ma i ol low-level output current 16 16 ma t a operating free-air temperature ?55 125 0 70 c note 3: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions ? sn5400 SN7400 unit parameter test conditions ? min typ max min typ max unit v ik v cc = min, i i = ?12 ma ?1.5 ?1.5 v v oh v cc = min, v il = 0.8 v, i oh = ?0.4 ma 2.4 3.4 2.4 3.4 v v ol v cc = min, v ih = 2 v, i ol = 16 ma 0.2 0.4 0.2 0.4 v i i v cc = max, v i = 5.5 v 1 1 ma i ih v cc = max, v i = 2.4 v 40 40 a i il v cc = max, v i = 0.4 v ?1.6 ?1.6 ma i os ? v cc = max ?20 ?55 ?18 ?55 ma i cch v cc = max, v i = 0 v 4 8 4 8 ma i ccl v cc = max, v i = 4.5 v 12 22 12 22 ma ? for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. all typical values are at v cc = 5 v, t a = 25 c. ? not more than one output should be shorted at a time.
sdls025b ? december 1983 ? revised october 2003 5 post office box 655303 ? dallas, texas 75265 switching characteristics, v cc = 5 v, t a = 25 c (see figure 1) parameter from (input) to (output) test conditions sn5400 SN7400 unit parameter (input) (output) test conditions min typ max unit (input) (output) min typ max t plh a or b y r l = 400 ? , c l = 15 pf 11 22 ns t phl a or b y r l = 400 ? , c l = 15 pf 7 15 ns recommended operating conditions (see note 4) sn54ls00 sn74ls00 unit min nom max min nom max unit v cc supply voltage 4.5 5 5.5 4.75 5 5.25 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.7 0.8 v i oh high-level output current ?0.4 ?0.4 ma i ol low-level output current 4 8 ma t a operating free-air temperature ?55 125 0 70 c note 4: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions ? sn54ls00 sn74ls00 unit parameter test conditions ? min typ ? max min typ ? max unit v ik v cc = min, i i = ?18 ma ?1.5 ?1.5 v v oh v cc = min, v il = max, i oh = ?0.4 ma 2.5 3.4 2.7 3.4 v v ol v cc = min, v ih = 2 v i ol = 4 ma 0.25 0.4 0.25 0.4 v v ol v cc = min, v ih = 2 v i ol = 8ma 0.35 0.5 v i i v cc = max, v i = 7 v 0.1 0.1 ma i ih v cc = max, v i = 2.7v 20 20 a i il v cc = max, v i = 0.4 v ?0.4 ?0.4 ma i os v cc = max ?20 ?100 ?20 ?100 ma i cch v cc = max, v i = 0 v 0.8 1.6 0.8 1.6 ma i ccl v cc = max, v i = 4.5 v 2.4 4.4 2.4 4.4 ma ? for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ? all typical values are at v cc = 5 v, t a = 25 c. not more than one output should be shorted at a time. switching characteristics, v cc = 5 v, t a = 25 c (see figure 1) parameter from (input) to (output) test conditions sn54ls00 sn74ls00 unit parameter (input) (output) test conditions min typ max unit (input) (output) min typ max t plh a or b y r l = 2 k ? , c l = 15 pf 9 15 ns t phl a or b y r l = 2 k ? , c l = 15 pf 10 15 ns
sdls025b ? december 1983 ? revised october 2003 6 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 5) sn54s00 sn74s00 unit min nom max min nom max unit v cc supply voltage 4.5 5 5.5 4.75 5 5.25 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v i oh high-level output current ?1 ?1 ma i ol low-level output current 20 20 ma t a operating free-air temperature ?55 125 0 70 c note 5: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions ? sn54s00 sn74s00 unit parameter test conditions ? min typ ? max min typ ? max unit v ik v cc = min, i i = ?18 ma ?1.2 ?1.2 v v oh v cc = min, v il = 0.8 v, i oh = ?1 ma 2.5 3.4 2.7 3.4 v v ol v cc = min, v ih = 2 v, i ol = 20 ma 0.5 0.5 v i i v cc = max, v i = 5.5 v 1 1 ma i ih v cc = max, v i = 2.7 v 50 50 a i il v cc = max, v i = 0.5v ?2 ?2 ma i os v cc = max ?40 ?100 ?40 ?100 ma i cch v cc = max, v i = 0 v 10 16 10 16 ma i ccl v cc = max, v i = 4.5 v 20 36 20 36 ma ? for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. ? all typical values are at v cc = 5 v, t a = 25 c. not more than one output should be shorted at a time. switching characteristics, v cc = 5 v, t a = 25 c (see figure 1) parameter from (input) to (output) test conditions sn54s00 sn74s00 unit parameter (input) (output) test conditions min typ max unit (input) (output) min typ max t plh a or b y r l = 280 ? , c l = 15 pf 3 4.5 ns t phl a or b y r l = 280 ? , c l = 15 pf 3 5 ns t plh a or b y r l = 280 ? , c l = 50 pf 4.5 ns t phl a or b y r l = 280 ? , c l = 50 pf 5 ns
sdls025b ? december 1983 ? revised october 2003 7 post office box 655303 ? dallas, texas 75265 parameter measurement information series 54/74 devices t phl t plh t plh t phl load circuit for 3-state outputs high-level pulse low-level pulse voltage waveforms pulse durations input out-of-phase output (see note d) 3 v 0 v v ol v oh v oh v ol in-phase output (see note d) voltage waveforms propagation delay times v cc r l test point from output under test c l (see note a) load circuit for open-collector outputs load circuit for 2-state totem-pole outputs (see note b) v cc r l from output under test c l (see note a) test point (see note b ) v cc r l from output under test c l (see note a) test point 1 k ? notes: a. c l includes probe and jig capacitance. b. all diodes are 1n3064 or equivalent. c. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. d. s1 and s2 are closed for t plh , t phl , t phz , and t plz ; s1 is open and s2 is closed for t pzh ; s1 is closed and s2 is open for t pzl . e. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o 50 ? ; t r and t f 7 ns for serie s 54/74 devices and t r and t f 2.5 ns for series 54s/74s devices. f. the outputs are measured one at a time with one input transition per measurement. s1 s2 t phz t plz t pzl t pzh 3 v 3 v 0 v 0 v t h t su voltage waveforms setup and hold times timing input data input 3 v 0 v output control (low-level enabling) waveform 1 (see notes c and d) waveform 2 (see notes c and d) 1.5 v v oh ? 0.5 v v ol + 0.5 v 1.5 v voltage waveforms enable and disable times, 3-state outputs 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v t w 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v v oh v ol figure 1. load circuits and voltage waveforms
package option addendum www.ti.com 24-apr-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples jm38510/00104bca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 00104bca jm38510/00104bda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 00104bda jm38510/07001bca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 07001bca jm38510/07001bda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 07001bda jm38510/30001b2a active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 jm38510/ 30001b2a jm38510/30001bca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 30001bca jm38510/30001bda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 30001bda jm38510/30001sca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/30001s ca jm38510/30001sda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/30001s da m38510/00104bca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 00104bca m38510/00104bda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 00104bda m38510/07001bca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 07001bca m38510/07001bda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 07001bda m38510/30001b2a active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 jm38510/ 30001b2a m38510/30001bca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 30001bca m38510/30001bda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 30001bda m38510/30001sca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/30001s ca
package option addendum www.ti.com 24-apr-2015 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples m38510/30001sda active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 jm38510/30001s da sn5400j active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 sn5400j sn54ls00j active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 sn54ls00j sn54s00j active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 sn54s00j SN7400d active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 7400 SN7400dg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 7400 SN7400n active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type 0 to 70 SN7400n SN7400n3 obsolete pdip n 14 tbd call ti call ti 0 to 70 SN7400ne4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type 0 to 70 SN7400n sn74ls00d active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ls00 sn74ls00dble obsolete ssop db 14 tbd call ti call ti 0 to 70 sn74ls00dbr active ssop db 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ls00 sn74ls00dg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ls00 sn74ls00dr active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ls00 sn74ls00dre4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ls00 sn74ls00j obsolete cdip j 14 tbd call ti call ti 0 to 70 sn74ls00n active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type 0 to 70 sn74ls00n sn74ls00ne4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type 0 to 70 sn74ls00n sn74ls00nsr active so ns 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 74ls00 sn74ls00nsrg4 active so ns 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 74ls00
package option addendum www.ti.com 24-apr-2015 addendum-page 3 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn74ls00psr active so ps 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ls00 sn74ls00psrg4 active so ps 8 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ls00 sn74s00d nrnd soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 s00 sn74s00de4 nrnd soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 s00 sn74s00n nrnd pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type 0 to 70 sn74s00n sn74s00n3 obsolete pdip n 14 tbd call ti call ti 0 to 70 sn74s00ne4 nrnd pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type 0 to 70 sn74s00n snj5400j active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 snj5400j snj5400w active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 snj5400w snj5400wa obsolete cfp wa 14 tbd a42 n / a for pkg type -55 to 125 snj5400wa snj54ls00fk active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 snj54ls00fk snj54ls00j active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 snj54ls00j snj54ls00w active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 snj54ls00w snj54s00fk active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 snj54s 00fk snj54s00j active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 snj54s00j snj54s00w active cfp w 14 1 tbd a42 n / a for pkg type -55 to 125 snj54s00w (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 24-apr-2015 addendum-page 4 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn5400, sn54ls00, sn54ls00-sp, sn54s00, SN7400, sn74ls00, sn74s00 : ? catalog: SN7400 , sn74ls00 , sn54ls00 , sn74s00 ? military: sn5400 , sn54ls00 , sn54s00 ? space: sn54ls00-sp note: qualified version definitions: ? catalog - ti's standard catalog product
package option addendum www.ti.com 24-apr-2015 addendum-page 5 ? military - qml certified for military and defense applications ? space - radiation tolerant, ceramic packaging and qualified for use in space-based application
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74ls00dbr ssop db 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 q1 sn74ls00dr soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 sn74ls00nsr so ns 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 q1 sn74ls00psr so ps 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 q1 package materials information www.ti.com 26-jan-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74ls00dbr ssop db 14 2000 367.0 367.0 38.0 sn74ls00dr soic d 14 2500 367.0 367.0 38.0 sn74ls00nsr so ns 14 2000 367.0 367.0 38.0 sn74ls00psr so ps 8 2000 367.0 367.0 38.0 package materials information www.ti.com 26-jan-2013 pack materials-page 2

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? 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